Test wrapper and test access mechanism co-optimization for system-on-chip
نویسندگان
چکیده
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrapper design problem at a time, i.e., either optimizing the TAMs for a set of pre-designed wrappers, or optimizing the wrapper for a given TAM width. In this paper, we address a more general problem, that of carrying out TAM design and wrapper optimization in conjunction. We present an efficient algorithm to construct wrappers that reduce the testing time for cores. Our wrapper design algorithm improves on earlier approaches by also reducing the TAM width required to achieve these lower testing times. We present new mathematical models for TAM optimization that use the core testing time values calculated by our wrapper design algorithm. We further present a new enumerative method for TAM optimization that reduces execution time significantly when the number of TAMs being designed is small. Experimental results are presented for an academic SOC as well as an industrial SOC.
منابع مشابه
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is therefore necessary for minimizing SOC testing time. We recently proposed an exact technique for co-optimization based on a combination of integer linear programming (ILP) and exhaustive enumeration. However, this approach...
متن کاملEfficient Wrapper/TAM Co-Optimization for SOC Using Rectangle Packing
The testing time for a system-on-chip(SOC) largely depends on the design of test wrappers and the test access mechanism(TAM).Wrapper/TAM co-optimization is therefore necessary to minimize SOC testing time . In this paper, we propose an efficient algorithm to construct wrappers that reduce testing time for cores. We further propose a new approach for wrapper/TAM co-optimization based on two-dime...
متن کاملWrapper/TAM Co-Optimization and Test Scheduling for SOCs Using Rectangle Bin Packing Considering Diagonal Length of Rectangles
This paper describes an integrated framework for SOC test automation. This framework is based on a new approach for Wrapper/TAM co-optimization based on rectangle packing considering the diagonal length of the rectangles to emphasize on both TAM widths required by a core and its corresponding testing time. In this paper, we propose an efficient algorithm to construct wrappers that reduce testin...
متن کاملContribution to Digital System Testing Methods
System-on-chip is an integrated circuit comprising of numerous functional cores which can be of various types. Testing of such diverse circuit is very complex problem. Test access to digital cores is ensured by core wrapper architectures. The paper presents two novel contributions to core test wrappers: (1) the set of optimization techniques for parallel interface to provide faster test applica...
متن کاملTest Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip
We describe an integrated framework for system-on-chip (SOC) test automation. Our framework is based on a new test access mechanism (TAM) architecture consisting of flexible-width test buses that can fork and merge between cores. Test wrapper and TAM cooptimization for this architecture is performed by representing core tests using rectangles and by employing a novel rectangle packing algorithm...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
- J. Electronic Testing
دوره 18 شماره
صفحات -
تاریخ انتشار 2001